That is true, although it's worth saying that (if I'm not mistaken) outside of patents we don't really know what the micro-ops do i.e. RISC possibly isn't the best descriptor.
The microarchitectural classification of a modern CPU is slightly murky, i.e. a modern x86 has a pipeline a la the first one to do so, but the way the CPU actually uses it is completely different (i.e. OoO, speculative etc.)
The microarchitectural classification of a modern CPU is slightly murky, i.e. a modern x86 has a pipeline a la the first one to do so, but the way the CPU actually uses it is completely different (i.e. OoO, speculative etc.)