"we will be implementing a 2-bit variant of SUBLEQ for demonstration purposes"
What they actually built was a 2-bit wide machine with one instruction. No, they can't run Doom, which they mention a lot.
There's a lot of hand-waving about memory, around page 10. They seem to have used a delay line, which is very slow; you have to wait for the bits you want to come around. That's been a classic problem with photonics. You can build gates, which is nice for switching packets, but how do you store data?
Much of the architectural discussion is about what you can do if memory is mostly ROM. They talk about fast-read, really slow write memory. Here's an article about building something like that.[2] It's a clunky technology. Writing involves on-chip heaters and switching memory cells back and forth from amorphous to crystalline. There's a long history of forgotten devices like that - photochromic memory, UV-erasable EEPROMS, rewritable DVDs, Ovonics, etc. All were superseded by something with better read-write properties.
The underlying device technology is not theirs. It's from the Cornerstone project.[1]
> You can build gates, which is nice for switching packets, but how do you store data?
Logic gates can be the fundamental building block. So if you can build logic gates, then you can use those to build flip flops (the basis of static RAM) which store data. Might not be the most efficient way (depending on your requirements) but it can be done.
Nit pick: SRAM is not built out of flip flops. It's carefully sized inverters and a whole lot of analog magic (writing a bit involves overpowering the inverters of the bit with larger drivers). You may be thinking of latch arrays.
The overpowering of the inverters is just an area efficient trick to make gates (the so-called wired-OR or wired-AND).
The SRAM memory cells are simpler than flip flops, they are just S-R latches (i.e. equivalent with a half of an M-S flip-flop) made from two gates (either NAND or NOR).
In any technology where static gates are possible SRAM memories are also possible.
However there are technologies where only dynamic gates are possible, i.e. gates that provide an output that is valid only during a clock pulse and which cannot remain valid indefinitely. Only in such technologies you cannot make SRAMs, but you can still make dynamic memories, which must consume energy all the time, for refreshing their content.
All the "analog magic" that you mention has only the purpose of making an SRAM array much denser than when implemented with the standard gates of a technology, but an implementation with standard gates is always possible and it may be chosen for certain register files, where high speed may be more important than the occupied area.
A 68k CPU has 68,000 transistors. If they have managed to produce all the building blocks of a CPU on a common optical process, why not build that?
Obviously this is only an easy option if the production is automated via lithography or something similar. If the process involves tweezering parts into place by hand, then a 2 bit SUBLEQ CPU is what you're gonna get...
Imagine this in a hypothetical setting such as Science Fiction. Where instead of an optical delay loop it's a fold in space or some other mechanism. Photonics and some sort of 'subspace' or toggled shift in reality? Maybe.
I agree though, I've never seen anything explain how to make this work well as a general computer with contemporary tech.
> They seem to have used a delay line, which is very slow; you have to wait for the bits you want to come around.
Macroscopic delay lines sure, but microscopic ones presumably can be on the order of a wavelength, if that's all that's needed. Not much time needed to come around in that case.
i don't know anything about optical computing, but a 2-bit wide one instruction machine can 100% run Doom. if it is turing complete it can run anything and SUBLEQ is turing complete
What they actually built was a 2-bit wide machine with one instruction. No, they can't run Doom, which they mention a lot.
There's a lot of hand-waving about memory, around page 10. They seem to have used a delay line, which is very slow; you have to wait for the bits you want to come around. That's been a classic problem with photonics. You can build gates, which is nice for switching packets, but how do you store data?
Much of the architectural discussion is about what you can do if memory is mostly ROM. They talk about fast-read, really slow write memory. Here's an article about building something like that.[2] It's a clunky technology. Writing involves on-chip heaters and switching memory cells back and forth from amorphous to crystalline. There's a long history of forgotten devices like that - photochromic memory, UV-erasable EEPROMS, rewritable DVDs, Ovonics, etc. All were superseded by something with better read-write properties.
The underlying device technology is not theirs. It's from the Cornerstone project.[1]
[1] https://www.mdpi.com/2076-3417/10/22/8201
[2] https://www.nature.com/articles/s41377-023-01213-3